On Demand Content
Evolving the Coverage-Driven Verification Flow (WHITE PAPER)
Achieving functional coverage closure is challenging and time-consuming with today's complex designs. Read how unique coverage-targeting algorithms in intelligent testbench automation tools reduce time to coverage closure by 90%.
Sponsored by: Mentor Graphics
Lowering Total System Power Using Xilinx FPGAs (CHALK TALK)
In this webcast, Chalk Talk host Amelia Dalton talks with Jameel Hussein of Xilinx about optimizing system-level power with FPGAs, and features and tools that simplify low-power design with Xilinx FPGAs.
Sponsored by: Xilinx
Pushing The Envelope in FPGA Design Using PlanAhead (CHALK TALK)
Want to have the best FPGA designs on the block? You have to push the technology to stay competitive. Join Amelia Dalton as she talks with Greg Daughtry of Xilinx in this Chalk Talk about pushing the envelope in FPGA design.
Sponsored by: Xilinx
EasyPath-6 FPGAs Deliver Lowest Total Product Cost in Six Weeks (CHALK TALK)
Confused about FPGA cost reduction? There are easy options for even the most sophisticated FPGAs. Join Amelia Dalton and Shekhar of Xilinx in this Chalk Talk about cost-reducing your Virtex FPGA design with EasyPath.
Sponsored by: Xilinx
Demystifying DO-254 (WHITE PAPER)
Interest in DO-254 first occurred in Europe and has since spread to the US commercial aircraft industry. If you are being asked about your company’s DO-254 direction and compliance, but have been overwhelmed with information on the subject, then this article is for you.
Sponsored by: Mentor Graphics
QuickLogic’s Visual Enhancement Engine (VEE™) Brings iridix® to Mobile Devices (WHITE PAPER)
The iridix algorithm was developed by Apical Limited to drastically enhance image quality by employing dynamic range compression. This innovative and patented technology is the result of more than a decade of research by Apical scientists based on how the human eye perceives image contrast under various lighting conditions.
Sponsored by: QuickLogic
Power Management in an Embedded Multiprocessor Cluster (WHITE PAPER)
Coherent microprocessor clusters, having localized instruction and data caches per CPU, require special techniques to maintain consistency between localized cache contents and their common address region. For embedded systems, designers typically apply snoop-based schemes to maintain memory coherence.
Sponsored by: MIPS
Developing Embedded Applications with ARM® Cortex™-M1 Processors in Actel IGLOO and Fusion FPGAs (WHITE PAPER)
Until recently, the embedded market has been primarily the domain of 8-bit microcontrollers. While embedded applications existed for 32-bit processors, they were limited to a few high-performance areas. The level of processing required for many embedded applications is increasing dramatically due to the convergence of communication and consumer applications and the delivery of higher levels of content, including video and high-end audio.
Sponsored by: Actel
Dual-Processor FPGA Designs Made Easier (CHALK TALK)
Thinking of using multiple processors on FPGA-based systems? Join Amelia Dalton as she demystifies dual-processor development with Rey Archide of Xilinx.
Sponsored by: Xilinx
Simplifying Processor-Based Designs in FPGAs (CHALK TALK)
Using processors in FPGAs? It doesn't have to be complicated. Join Amelia Dalton as she chats with Steve Wenande of Xilinx about Simplifying Processor-Based Designs in FPGAs.
Sponsored by: Xilinx
ZeBu™: A Unified Verification Approach for Hardware Designers and Embedded Software Developers (WHITE PAPER)
Moore’s law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically “break” existing design flows. Fortunately for EDA users, the same shrinking geometries that make their design problems tougher are also helping to improve the performance for their EDA tools.
Sponsored by: EvE
Designing Enterprise-Class Wireless Access Points and Residential Gateways: Meeting the Price, Performance, and Power Challenges of 802.11n with the PowerPC 405EX (WHITE PAPER)
The higher data rates and advanced services expected of next-generation 802.11n (Wi-Fi) and WiMAX-based wireless Enterprise Access Points (APs) and residential gateways require engineers to reconsider how they approach AP design.
Sponsored by: AMCC
Power Estimation in High-Level DSP Design Flow (CHALK TALK)
Want your DSP design to consume less power? Join Amelia Dalton as she talks with Tim Vanevenhoven of Xilinx about new methods for estimating and reducing power consumption in FPGA-based DSP designs.
Sponsored by: Xilinx
OpenComRTOS: Reliable Performance for Heterogeneous Real-time Systems with a Small Code Size (WHITE PAPER)
OpenComRTOS is one of the few Real-Time Operating Systems for embedded systems that was developed using formal modeling techniques. The goal was to obtain a proven trustworthy component with a clean architecture which delivers high performance on a wide variety of networked embedded systems, ranging from single processor to distributed systems.
Sponsored by: Altreonic
Confirma™: The Next Era Of Prototyping (CHALK TALK)
Struggling with FPGA prototyping boards? Join Amelia Dalton as she talks with Juergen Jaeger of Synopsys about the Next Era of Rapid Prototyping.
Sponsored by: Synopsys